The present invention relates to an image sensing apparatus, an image processing apparatus, and an image sensing system and, more particularly, to an image sensing apparatus suitable as a camera head of a head-detachable camera which comprises a charge-coupled device and its controller, an image processing apparatus suitable as a signal processing apparatus of the head-detachable camera for performing various signal processes on signals obtained by the camera head and generating image signals, and an image sensing system, as the head-detachable camera, comprising the above image sensing apparatus and image processing apparatus which can be separated.
Conventionally, there is a head-detachable camera comprising a camera head having a charge-coupled device (CCD) and a controller for the CCD and a signal processing unit, which can be separated from the camera head, for performing various signal processes on signals obtained by the CCD of the camera head and generating image signals, where the camera head and the signal processing unit are connected by a cable to configure the head-detachable camera. In such the head-detachable camera, there is a merit that the camera head, which is a substantial image sensing unit, can be down-sized and lightened by separately configuring the signal processing unit. Further, there is a head-detachable camera to which a plurality of interchangeable camera heads, such as a panfocus camera and a zoom camera can be connected. In such the head-detachable camera, the signal processing unit is configured as a board with an image memory, to be installed on a computer, thereby an image sensed by the camera head can be instantaneously inputted to the computer.
An example of a head-detachable camera is described below.
FIG. 17 is a block diagram illustrating a configuration of a conventional image sensing system.
In FIG. 17, reference numerals 1140 and 1150 denote camera heads (will be described later in detail); 1200, an image processing unit; 1400, a host terminal. The camera head 1140 or 1150 is connected to the image processing unit 1200 via a cable 1109. The image processing unit 1200 is connected to the host terminal 1400 via a bus interface (I/F) 1208. The image processing unit 1200 and the camera head 1140 or 1150 are controlled from the host terminal 1400 via the bus I/F 1208.
The camera head 1140 is a monofocal CCD camera having 200,000 pixels, and the camera 1150 is a zoom CCD camera having 400,000 pixels.
First, a configuration of the monofocal CCD camera 1140 will be explained.
Reference numeral 1106 denotes a system controller which comprises a one-chip microcomputer having CPU, ROM, RAM, a control port, a communication port, and so on. The system controller 1106 controls each unit of the camera head 1140, and performs bidirectional communication with the image processing unit 1200.
Reference numeral 1101 denotes a lens unit having an object lens, a focus lens, and a focus ring for moving the focus lens manually; 1102, an iris unit for adjusting the quantity of incoming light through the lens system 1101, and the iris unit 1102 has an iris diaphragm and an iris ring for moving the iris diaphragm manually; 1103, an image sensing device, such as a CCD, for photo-electric conversing the image passed through the lens unit 1101 and the iris unit 1102 into electric signals, and the image sensing device 1103 has 200,000 image sensing elements; and 1105, an image sensing device driver, such as a timing signal generator (TG), which controls charging operation, reading operation, and resetting operation of the image sensing device 1103 in accordance with the number of pixels. Shutter speed can be changed by controlling the TG 105 from the system controller 1106 via a control line 1110.
Reference numeral 1108 denotes a synchronizing signal generator (SSG) which generates image synchronizing signals 1112, such as a horizontal synchronizing signal (HD), a vertical synchronizing signal (VD), and an image clock signal, on the basis of a clock signal from the TG 1105; and 1104, a sample-and-hold and automatic gain control circuit (S/H• AGC) which performs sample-and-hold operation for reducing noises of stored charges as well as adjusts gain for an image signal, and outputs an image signal 1114. The gain for an image signal can be adjusted by controlling the S/H• AGC 1104 from the system controller 1106 via a control line 1111. Reference numeral 1113 denotes a data and data control line for performing bidirectional communication between the camera head 1140 and the image processing unit 1200, and the line 1113 is connected to a serial communication port of the system controller 1106. Reference numeral 1107 denotes a connector which can be connected and disconnected to/from the cable 1109.
Next, a configuration of the camera head 1150 will be explained. The differences between the camera heads 1140 and 1150 are a zoom lens unit 1121, an iris unit 1122, and an image sensing device 1123. Other units and elements of the camera head 1150 are the same as those of the camera head 1140, thus the explanation of those are omitted.
The zoom lens unit 1121 comprises an object lens, a focus lens, a focus motor for moving a focus ring, a zoom lens, a zoom motor for moving a zoom ring. Power zooming and auto-focusing can be realized by controlling the zoom lens unit 1121 from the system controller 1106 via a control line 1124.
The iris unit 1122 adjusts the quantity of incoming light through the lens unit 1101, and has an iris diaphragm and an iris motor for moving an iris ring. By controlling the iris unit 1122 from the system controller 1106 via a control line 1125, open/close operation of the iris diaphragm is controlled. The system controller 1106 controls the aperture, shutter speed, and gain for the S/H• AGC 1104 so as to keep data values indicating brightness of an object image sent from the image processing unit 1200 substantially constant, thereby an automatic exposure control can be realized. Further the image sensing device 1123, such as a CCD, performs photoelectric conversion on the image passed through the lens unit 1121 and the iris unit 1122 and converts into electric signals. The image sensing device 1123 has 400,000 image sensing elements.
Next, the image processing unit 1200 will be explained.
Reference numeral 1250 denotes a system controller which comprises a one-chip microcomputer having CPU, ROM, RAM, a control port, a communication port, and so on. The system controller 1250 controls each unit of the image processing unit 1200, performs automatic white balance control, and communicates with the camera head 1140 or 1150 and with the host terminal 1400 via the bus I/F 1208. Further, it interprets a command from the host terminal 1400, and performs an operation requested by the host terminal 1400.
Reference numeral 1201 denotes an A/D converter for converting the image signal 1217 transmitted via the cable 1109 from the camera head 1140 or 1150 into a digital image signal 1218; and 1202, a signal processing circuit for converting the digital image signal 1218 into a standardized digital image signal 1219. The signal processing circuit 1202 generates and transmits an interruption signal for informing of data indicating brightness of an object to be used for exposure control, white balance data for white balance control, and focus data for focus control to the system controller 1250 at the period of a vertical synchronization signal. When the system controller 1250 acknowledges the interruption, it reads the brightness data, the white balance data, and the focus data via a switch 1203 and a serial data line 1223 and writes these data in the RAM of the system controller 1250.
Further, reference numeral 1204 denotes an encoder for converting the standardized digital image signal 1219 to a multiplexed composite signal 1221 and it outputs the composite signal 1221 to an image output connector 1210; 1206, an image memory for storing digital image signals from the signal processing circuit 1202 and a scan rate converter (SRC) 1207; 1205, a memory controller for performing read/write control from/to the image memory 1206; and 1207, the scan rate converter (SRC) for converting a digital image signal 1213 in the image processor 1200 into a digital image signal 1214 to be outputted to the host terminal 1400 so as to absorb the difference in length-to-breadth ratio between a frame image represented by the digital image signal 1213 and a frame image suitable for the host terminal 1400.
The switch 1203 selects either the standardized digital image signal 1219 from the signal processing circuit 1202 or a digital image signal 1216 stored in the image memory 1206 to be outputted as an output 1225 to the encoder 1204, and it is controlled by the system controller 1250 via a control line 1224.
Further, the bus interface (I/F) 1208 is connected to a bus of a computer as the host terminal 1400, and it interfaces between the host terminal 1400 and the image processing unit 1200 to communicate the digital image signal 1214 and a control data 1226 as well as to control the memory controller 1205 and the SRC 1207 by the host terminal 1400.
Reference numeral 1215 denotes image synchronizing signals of the image processing unit 1200 which correspond to the image synchronizing signals from the camera head 1140 or 1150, and the signals enter the signal processing circuit 1202, the memory controller 1205, and the encoder 1204.
Reference numeral 1222 denotes serial data and data control line for performing bidirectional data communication between the camera head 1140 or 1150 and the image processing unit 1200, and it is connected to a serial data port of the system controller 1250.
Reference numeral 1226 denotes parallel data and data control line for performing bidirectional data communication between the host terminal 1400 and the image processing unit 1200, and it is connected to a control port of the system controller 1250.
A user can select a camera head in accordance with his/her utilization purpose by interchanging camera heads. When interchanging camera heads, parameters have to be set in the signal processing circuit 1202 in accordance with the type of the connected camera head. For example, the number of pixels used in the image sensing device 1103 of the panfocus camera 1140 is 200,000, and that of the image sensing device 1123 of the zoom camera 1150 is 400,000. In this case, the signal processing circuit 1202 is initialized in 200,000 pixel mode when the camera head 1140 is connected, and in 400,000 pixel mode when the camera head 1150 is connected.
In the configuration of the above image sensing system, an exclusive data line for informing the image processing unit 1200 of information, such as the number of pixels, of the image sensing device 1103 or 1123 of the connected camera head 1140 or 1150 from the camera head 1140 or 1150 is provided in the cable 1109. The signal processing circuit 1202 is initialized based on the information of the image sensing device 1103 or 1123 which is obtained via the exclusive data line.
However, there is an image sensing system which does not have an exclusive data line for notifying information on an image sensing device. An example of such the image sensing system is described below.
A configuration and operation of a head-detachable camera which does not have an exclusive data line for notifying information on the image sensing device will be explained with reference to FIG. 18. In FIG. 18, reference numeral 201 denotes a camera head; and 202, an image processing unit. In the camera head 201, reference numeral 203 denotes a CCD for converting an optical signal which is inputted through a lens (not shown) into an electric signal. A color image signal can be obtained by using a color filter attached on the surface of the CCD 203. Reference numeral 204 denotes a timing signal generator (TG) for generating various timing signals for reading an image signal from the CCD 203; and 205, an automatic gain controller (AGC) for adjusting gain for the image signal read from the CCD 203. The AGC 205 and the TG 204 are controlled by a camera control CPU 206, so that shutter speed and automatic exposure can be controlled.
Further, the CPU 206 exchanges commands and data with a signal processing control CPU 213 of the image processing unit 202. The commands and data are inputted to a vertical interval data signal (VIDS) processing unit 207 as serial data. The VIDS processing unit 207 has a function of multiplexing the input serial data in a vertical blanking period of the image signal obtained form the AGC 205 and outputting it, and a function of separating serial data from a horizontal synchronizing signal and a vertical synchronizing signal out of the composite synchronizing signal, sent from the image processing unit 202, to which serial data is multiplexed, then outputting the serial data to the camera control CPU 206 and the vertical and horizontal synchronizing signals to the TG 204. Note, the VIDS is a method for multiplexing digital data in a non-image portion of a vertical blanking period. The VIDS processing unit 207 of the camera head 201 multiplexes data in the vertical blanking period of an image signal, and, a VIDS processing unit 210 of the image processing unit 202 multiplexes data in all the areas of the synchronizing signals, and these VIDS processing units transfer the obtained composite signals to each other. The reason for employing the VIDS method for communication between the camera head 201 and the image processing unit 202 is to minimize the number of connection lines between them.
Each block of the camera head 201 operates in accordance with a reference clock signal provided from the image processing unit 202. For example, if the CCD 203 has 410,000 pixels and is driven in the NTSC video rate, the frequency of the reference clock signals has to be 14.31818 Mhz (4 frequency subcarrier (fsc)), and the clock signal of this fixed frequency is always provided from the image processing unit 202.
In the image processing unit 202, reference numeral 210 denotes the VIDS processing unit. The VIDS processing unit 210 has functions which are opposite to the VIDS processing unit 207 of the camera head 201, i.e., a function of multiplexing serial data inputted from the signal processing control CPU 213 in a composite synchronizing signal generated by a synchronizing signal generator 218, and a function of separating serial data from an image signal out of a multiplexed image signal transmitted from the camera head 201, then outputting the serial data to the signal processing control CPU 213 and the image signal to a signal processing circuit 211.
The synchronizing signal generator 218 is configured in correspondence with the camera head 201, and it generates horizontal and vertical synchronizing signals corresponding to the video method employed by the camera head 201 (e.g., NTSC, PAL) on the basis of a reference clock signal provided from a clock generator 217. If the camera head 201 is driven by the NTSC video rate, for example, horizontal and vertical synchronizing signals corresponding to the NTSC video rate are generated. In this case, a clock signal of 14.31818 Mhz is provided from the clock generator 217.
The signal processing circuit 211 performs analog-digital conversion on the input image signal into a digital signal, generates three lines of signals by using one-horizontal-line delay circuits. Further, it performs matrix operation on the signals of three lines, generates R, G and B color signals and multiplexes the R, G and B color signals in time division. Furthermore, it also performs white balance processing and γ correction, then generates color difference signals R-Y and B-Y and a luminance signal Y by performing color difference matrix operation. On the luminance signal Y, aperture correction in the horizontal and vertical directions is performed. The color difference signals and the luminance signal are outputted to a memory 212 as digital signals and to an encoder 214 where the signals are digital-analog converted into analog signals. Then, a synchronizing signal is added to the luminance signal Y, further color difference signals are added to it to generate a composite video signal. The generated composite video signal is outputted from an output terminal 220 to outside.
Reference numeral 215 denotes a bus controller for exchanging data with a computer bus 216, such as an industry standard architecture (ISA) bus and a peripheral component interconnect (PCI) bus, for example, which is a standard bus for computers, and it is connected to the computer bus 216 via address, data, input/output, write, read, interruption, clock, power, and ground signal lines, for example. A specific address is assigned to the bus controller 215, and the bus controller 215 decodes the address signal inputted from the computer bus 216 and controls transmission and reception of data to/from the signal processing control CPU and data-read operation from the memory 212 in accordance with the value of the data signal inputted when the address of the address signal matches the address of the bus controller 215. Accordingly, it is possible to control the image sensing system from a main CPU of a computer (not shown) via the computer bus 216.
In the image sensing system which does not have an exclusive data line for informing of information on an image sensing device as described above, the camera head and the signal processing unit are configured separately, thereby the camera head is down-sized, as well as interchange of plural kinds of camera heads having different functions, such a zoom function, becomes possible. However, there is a limitation that the CCD used in each interchangeable camera head must have the same number of pixels and must be operated at the same video rate. This is because if the number of pixels and the video rate used in the CCD are changed, speed of reading signals from the CCD has to be changed, and a processing clock rate in the signal processing unit also has to be changed accordingly.
Further, if the video rate changes, so does the resolution, thus frequencies of the synchronizing signals used in the camera head and the signal processing unit have to be changed. In order to do so, the signal processing unit has to recognize the number of pixels and the video rate of the camera head currently connected to the signal processing unit, and conform to them while operating the camera head. In the conventional image sensing system as shown in FIG. 18, however, since communication between the camera head 201 and the image processing unit 202 is performed with VIDS signals, there is a problem in which the communication can not be performed properly until the number of the pixels and the video rate of the CCD 203 in the camera head 201 is clearly identified and the image processing unit 202 conforms to them.
Further, in the image sensing system using an exclusive data line, when a user want to performs image sensing operation by using different camera heads, the use has to detach a currently connected camera head from the image processing unit then attach another camera, which is troublesome.